A memory cell array of, for example, a read-only memory (ROM), typically includes a plurality of memory cells arranged in rows and columns. Word lines typically extend along and are connected to the rows of the memory cells, while bit lines extend along and are connected to the columns of the memory cells. Typically, each memory cell comprises a transistor, e.g., a floating gate transistor, having a gate electrode connected to a word line, a source electrode connected to a signal ground, and a drain electrode connected to a bit line. To read data from a selected memory cell, the bit line to which the selected memory cell is connected to a sense amplifier and a word line to which the selected memory cell is connected is driven by a word line voltage.
Traditional single-bit ROM memory cells include a transistor having a threshold voltage that is set at one of two levels so that the memory cell stores one bit of data. To store more data, "multi-level" (or "multi-bit") devices have been proposed that utilize more than two threshold voltage levels to allow a signal memory cell to store multiple bits of data.
Various types of multi-level memories are possible. In one type, the gate length or gate width of the transistor of each memory cell is varied so that the current flowing when the memory cell is accessed may be set at various values. In other types of multilevel memories, the quantity of impurity ions injected into the metal oxide semiconductor (MOS) transistor of each memory cell is varied so that the threshold voltage of the MOS transistor may be set at various values.
FIG. 1 illustrates relationships between predetermined word line voltage thresholds WL0-WL2 and threshold voltage distributions Vth1-Vth4 for a multi-bit ROM. Each memory cell of multi-bit ROM may be classified as having one of four logic states 00-11, based on the relationship of its threshold voltage to the word line voltage level thresholds WL0-WL1.
FIG. 2 is a diagram showing reference voltages applied to a word line in a memory device such as the memory device 1 illustrated in FIG. 3 during a data reading operation for a multi-bit memory cell. While the word line is driven at a first word line voltage WL0, a sense amplifier circuit 17 detects whether a current (cell current) flows through the selected memory cell. Next, a second word line voltage WL1 higher than the first word line voltage WL0 is applied to the word line while the sense amplifier 17 determines whether a cell current flows through the selected memory cell. A third word line voltage WL2 higher than the first and second word line voltages WL0, WL1 is then applied to the word line while the sense amplifier determines whether a cell current flows through the memory device. As is known to those skilled in the art, the word line voltage at which the memory cell begins to exhibit current flow indicates the logic state of the memory cell. Generally, it is very important that the word line voltages WL0-WL2 are precisely controlled to prevent data sensing errors.
A typical multi-level memory device 1, illustrated in FIG. 3, includes an array 10 of multi-bit memory cells connected to word lines and bit lines (not shown). The word lines are selected by a pre row decoder circuit 11 and a block decoder circuit 12 in response to an address Ai applied thereto. A word line voltage generating circuit 13 generates a word line voltage VP and applies it to a selected word line via the pre-row decoding circuit 11 and the block decoder circuit 12. The voltage VP has different voltage levels, for example, the word line voltages WL0, WL1, WL2 illustrated in FIG. 2. The word line voltage generating circuit 13 receives a power supply voltage VCC/VPP from a voltage source 14, and generates the word line voltage VP therefrom. A bit line of the array 10 is selected by a column decoder circuit 15 and a column pass gating circuit 16, and a sense amplifier circuit 17 connected to the selected bit line detects whether a cell current flows in a memory cell connected to the selected bit line.
A conventional word line voltage generating circuit 13 is illustrated in FIG. 4. The structure of and exemplary operations for the word line voltage generating circuit 13 will be described below with reference to FIGS. 4 and 5. As shown in FIG. 5, when a signal STB is at a high level and signals NO.sub.-- ACT1, NO.sub.-- ACT2 and NO.sub.-- ACT3 are low, an output node ND1 is grounded through an NMOS transistor 48. First, second and third word line voltage generators 50, 51 and 52 are disabled because NMOS transistors 46 and 47 in the generators 50, 51 and 52 are turned off and PMOS transistors 41 in the generators 50, 51 and 52 are turned on.
A data reading operation begins when the signal NO.sub.-- ACT1 goes to a high level from a low level, while the signals NO.sub.-- ACT2 and NO.sub.-- ACT3 continue to remain at a low level. This causes the PMOS transistor 41 in the first word line voltage generator 50 to turn off and the NMOS transistors 46 and 47 to turn on. As a result, the node ND1 is pulled up through action of a PMOS transistor 43 of the first word line voltage generator 50.
As voltage at the output node ND1 increases, the gate voltage of a PMOS transistor 45 also increases. When the gate voltage of the PMOS transistor 45 exceeds a reference voltage VREF, the PMOS transistor 43 is turned off. Thus, the node ND1 voltage VP is regulated to a voltage: ##EQU1##
The second word line voltage generator 51 and the third word line voltage generator 52 operate in a similar manner in response to the signals NO.sub.-- ACT2 and NO.sub.-- ACT3, respectively. The second word line voltage generator 51 regulates the voltage VP to: ##EQU2## and the third word line voltage generator 52 regulates the output voltage VP to: ##EQU3## where the resistors R1, R2 and R3 have the relationship of R1&lt;R2&lt;R3.
Another conventional word line voltage generating circuit 13 is depicted in FIG. 6. The structure of and exemplary operations for the word line voltage generating circuit 13 of FIG. 6 will be described below with reference to FIGS. 6 and 7.
When a signal STB is at a high level, and a signal NO.sub.-- ACT is at a low level, an output node ND2 is grounded through an NMOS transistor 58 and the word line voltage generating circuit 13 is disabled, as a PMOS transistor 51 is turned on and NMOS transistors 56 and 57 are turned off.
When the signal STB and the signal NO.sub.-- ACT go to a high level, the node ND2 is pulled up through a PMOS transistor 53 because a gate voltage VREF.sub.-- V1 of an NMOS transistor 54 is higher than the gate voltage of an NMOS transistor 55. When the gate voltage of the NMOS transistor 55 exceeds the voltage VREF.sub.-- V1, the PMOS transistor 53 is turned off. Thus, the node ND2 is regulated to a voltage: ##EQU4##
As shown in FIG. 7, the voltage VREF.sub.-- V is varied, changing from a voltage VREF.sub.-- V1 to a voltage VREF.sub.-- V2 to a voltage VREF.sub.-- V3. At these set points, the node ND2 voltage may be expressed as: ##EQU5##
Yet another conventional word line voltage generating circuit 13 is depicted in FIG. 8. The structure of and exemplary operations for the word line voltage generating circuit 13 if FIG. 8 will be described below with reference to FIGS. 8 and 9.
When signals STB, STG2 and STG3 are at a high level and a signal NO.sub.-- ACT is at a low level, an output node ND3 is grounded through an NMOS transistor 68, a PMOS transistor 61 is turned on and NMOS transistors 66 and 67 are turned off, disabling the word line voltage generating circuit 13. When the signal STB next goes to a low level and the signal NO.sub.-- ACT goes to a high level, a data reading operation is started. The signals STG2 and STB3 continue at a high level turning on PMOS transistor 63, causing the voltage at the output node ND3 to increase. When the gate voltage of an NMOS transistor 65 exceeds the gate voltage of an NMOS transistor 64, that is, a reference voltage VREF, the PMOS transistor 63 turns off. As a result, the node ND3 voltage VP is regulated to a voltage: ##EQU6##
Similarly, when the signal STG2 becomes low while the signal STG3 remains high, the gate voltage of the NMOS transistor 65 falls below the reference voltage VREF. This turns the PMOS transistor 63 on so that the voltage VP at node ND3 increases. The voltage at node ND3 thus is stabilized at a new set point: ##EQU7##
Similarly, when the signals STB, STG2 and STG3 are all low: ##EQU8##
Because memory cell threshold voltages may vary due to process variations, word line voltage may need to be varied to correspond to such a threshold voltage variation to ensure that data reading operations can be performed reliably. To address such variations, the reference voltage level or resistance of resistors in the conventional word line voltage generating circuits 13 illustrated in FIGS. 4, 6 and 6 typically must be readjusted at a wafer level stage. This can increase cost and introduce manufacturing delays.